Application Programming Interface (SciEngines API)
The main purpose of the SciEngines API is to interface single and multiple FPGAs in a massively parallel architecture as simple and easy as possible. We intended to provide an infrastructure for your FPGA designs which is powerful enough to transport the benefits of a massively parallel architecture without raising the complexity of your design.
Therefore, we provide a simple interface which makes the idiosyncratic implementation of the physical layers disappear, and provides a high-level view into our machines in which details do not get in the way of your work.
To efficiently use SciEngines RIVYERA, the computational problem or algorithm is split into two general parts. One part is the strict software (front-end) part which remains on the integrated host PC inside the RIVYERA machine. The other part is the core algorithm which is accelerated by using the FPGAs on a single RIVYERA machine or even on multiple RIVYERA machines.
In general, the software part can be considered as a front-end for the user, or as a data interface to provide the resources for the FPGA accelerated parts. Also simple pre- or postcomputations are ideal for this part. The RIVYERA Host-API offers rich interface functions which are easily adaptable into existing code.
The second part implements the acceleration, flow control and multiple processing elements to solve the computational problem. The RIVYERA Machine-API offers useful adequate functions which easily allow you to implement the key parts of the algorithm. To support the development process, it allows an implementation without the programmer having to take care of low level communication and multiplication of processing elements.
Please find additional documentation for download below:
API hostside: C/C++
API hostside: Java
API FPGAside: VHDL
API simulation in software - Hardware/Software Co-Design