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The original 'massively parallel FPGA-computer'

120 Spartan-3 1000 FPGAs for number-crunching tasks


COPACOBANA, the Cost-Optimized Parallel Code Breaker, is an affordable FPGA-based high-performance computer, which is optimized for running cryptanalytical algorithms. Generally, COPACOBANA is suitable for parallel computation problems that have low communication requirements and, in addition to cryptanalysis, may also be applied to bioinformatics or other applications in the areas of financial mathematics or logistics. For applications with higher communication requirements, the new RIVYERA model provides enhanced functionality.


Key features


  • 120 Xilinx Spartan-3 1000 FPGAs
  • 64-bit data, 16-bit address bus
  • 120 mio system gates, 921k slices total
  • 442k bit block RAM and 24 18x18 multipliers per FPGA
  • 600W power usage; military-grade hardware possible
  • Up to 4000 PCs performance for specific algorithms


Technology Overview
Blazing Architecture

The 64-bit data and 16-bit address bus provides a maximum bus performace

Maximum Power for Minimum Price

Using the Xilinx Spartan-3 1000 chip, COPACOBANA ist capable of providing a maximum of computing performance for affordable costs.

Platform independent Host-API

Featuring a platform independent Host-API based on Java (C/C++ optional), COPACOBANA ensures to support nearly every host platform. An easy to use communication framework together with a demo application enables rapid integration of target applications and algorithms.

Schematic Overview
sample configuration
COPACOBANA – The Green Machine

Greener HPC

Computing power is not only about performance – it’s an environmental issue, too, which in turn also has an impact on the running costs. Of course, we want our computing jobs done as fast as possible, but huge computer clusters hunger for a huge amount of energy. Running a computation on a cluster will decrease computation time but increase energy consumption on a bigger rate then performance is gained. This additional energy is translated into additional heat, which in turn increased energy usage due to additional cooling requirement. Switching to GPU computing unfortunately doesn't solve this issue since the higher performance of graphics cards - when compared to CPUs - is also coupled with high energy requirements. 
The COPACOBANA on the other hand is a very energy efficient architecture. FPGA based computation maximizes the utilisation of the chip area and the user can implement solely the needed functional units while avoiding superfluous but energy consuming functionalities that are standard for a CPU or GPU. Furthermore, each FPGA in the COPACOBANA machine is driven with minimal control-overhead. This way, oftentimes thousands of PCs performance is achieved with only 600W of power consumption.

Simply do the math on kWh saved per year - comparing a COPACOBANA with a PC or GPU cluster of similar performance. You will not only see a financial impact of tens of thousand US$ per year but you will also be assured to have cut your computation's environmental impact by more than 95%. There is no high-performance computing architecture that is more energy efficient with a "greener" profile and lower total cost of ownership.

COPACOBANA in Cryptology

A highly parallelizable problem and extremely suitable application for the COPACOBANA S3-1000 is DES cracking: With more than 60 x 10^9 keys per second, an exhaustive key search of the Data Encryption Standard (DES) takes no longer than a week on average. Even though DES is not considered a secure encryption anymore, it is oftentimes used for benchmarking the performance of different architectures. Obviously, other ciphers can be attacked, too, and the COPACOBANA is referenced in a variety of cryptographic publications. For details on the history of the COPACOBANA as a cryptology platform, please visit www.copacobana.org (mirror). For more information on SciEngines cryptanalysis capabilities, please see our solutions page.

Technical Specifications
In the box
  • Rack mounting hardware
  • Power cords
  • I/O cable
  • Printed and electronic documentation
  • Drivers and Utilities CD–ROM

  • Xilinx Spartan–3 XC3S1000

  • optional: Xilinx Virtex–4
  • optional: Xilinx Spartan–3
  • offered fpga depends on configuration

  • 64 Bit data
  • 16 Bit adress
  • 20 Slots
I/O connections
  • optional: 10⁄100⁄1000BASE–T (Gigabit) RJ–45 Ethernet interface (supporting jumbo frames)
  • optional: USB 1.0
  • optional: USB 2.0
  • onboard JTAG–Port for service
  • offered interface depends on configuration
Rack support
  • Fits EIA–310–D–compliant, industry–standard four–post racks and cabinets: 19 inches wide, 24 to 36 inches deep front–to–back cooling for rack enclosure
  • front–to–back cooling for rack enclosure
  • Support for square–hole racks or threaded racks based on mounting kit selection

Electrical requirements
  • Output power: 800W
  • Line voltage: universal input (100V to 240V AC), power factor corrected
  • Maximum input current: 16.0A (100V to 120V) or 8.0A (200V to 240V)
  • Frequency: 50Hz to 60Hz, single phase

Environmental requirements
  • Operating temperature:
    -10°C to 50°C (14°F to 122°F)
  • Humidity (non condensing):
    10% to 90% RH

Size and weight
  • Height: 5.19 inches (13.2 cm)
  • Width: 17.6 inches (44.7 cm) for mounting in standard 19–inch rack
  • Depth: 32 inches (84.0 cm)
  • Weight: 31.7 pounds (14.4 kg) base configuration; 38.3 pounds (17.4 kg) for special version
Software included
  • JAVA
  • optional: C/C++