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COPACOBANA V4-SX35

 


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DSP-optimized reconfigurable architecture

Virtex based variant of the original COPACOBANA

 

COPACOBANA V4-SX35, the Cost-Optimized Parallel COde Breaker, is an FPGA-based machine which is optimized for running cryptanalytic algorithms that can take advantage of a high amount of DSPs and the possibility to execute a multiply-add or accumulate function every clock at high frequencies. This machine consists of 128 FPGAs each with 192, 500MHz Xtreme-DSP-Cores giving you performace you never expect from a parallel computer.

Key features

copacobana_virtex4sx35

  • 128 Virtex-4 SX35 FPGAs per machine
  • 24'576 XtremeDSP Slices at up to 500 MHz total
  • 3456k bit block RAM per FPGA
  • 1800W power usage; military-grade hardware possible
  • Best DSP/$ ratio of all Virtex FPGAs


This reconfigurable parallel computer comes without external memory but provides a high throughput bus. Dataflow dominated and computation intensive target applications of naturally parallel problems fit perfectly to this architecture. DES and ECC cracking are such parallelizable problems: An exhaustive key search of the Data Encryption Standard (DES) takes  only a few days on average with COPACOBANA V4-SX35. Other ciphers can be attacked too, and COPACOBANA V4SX35 can also be used for parallel computing problems outside cryptanalysis like bioinformatics alignment (e.g. Smith-Waterman, Motif Search), Logistics Optimization (e.g. Simplex) and many others.

Technology Overview
Architecture Overview

The 32-bit data and 16-bit address bus provides a maximum bus performace

Maximum Power

Using the Xilinx Virtex–4 SX35 chip, COPACOBANA Virtex–4 SX35 is capable of providing a maximum of computing performance for affordable costs.

Platform independent Host-API

Featuring a platform independent Host-API based on Java, COPACOBANA Virtex–4 SX35 ensures to support nearly every host platform. An easy to use communication framework together with a demo application enable rapid integration of target applications and algorithms.

Technical Specifications
In the box
  • COPACOBANA
  • Rack mounting hardware
  • Power cords
  • I/O cable (depends on option)
  • Printed and electronic documentation
  • Drivers and Utilities CD–ROM

FPGA
  • Xilinx Virtex–4 SX35 (XC4VSX35)

Host–Controller
  • optional: Xilinx Virtex–4
  • optional: Xilinx Spartan–3
  • offered fpga depends on configuration

Backplane
  • 32 Bit data
  • 16 Bit address
  • 16 Slots + 1 Controller-Slot
I/O connections
  • optional: 10⁄100⁄1000BASE–T (Gigabit) RJ–45 Ethernet interface (supporting jumbo frames)
  • optional: USB 1.0
  • optional: USB 2.0
  • onboard JTAG–Port for service
  • offered interface depends on configuration
Rack support
  • Fits EIA–310–D–compliant, industry–standard four–post racks and cabinets: 19 inches wide, 24 to 36 inches deep front–to–back cooling for rack enclosure
  • front–to–back cooling for rack enclosure
  • Support for square–hole racks or threaded racks based on mounting kit selection

Electrical requirements
  • Output power: 1500W
  • Line voltage: universal input (100V to 240V AC), power factor corrected
  • Maximum input current: 16.0A (100V to 120V) or 8.0A (200V to 240V)
  • Frequency: 50Hz to 60Hz, single phase

Environmental requirements
  • Operating temperature:
    -10°C to 50°C (14°F to 122°F)
  • Humidity (non condensing):
    10% to 90% RH

Size and weight
  • Height: 13.2 cm (5.19 inches)
  • Width: 44.7 cm (17.6 inches) for mounting in standard 19–inch rack
  • Depth: 84.0 cm (32 inches)
  • Weight: 14.4 kg (31.7 pounds) base configuration; 38.3 pounds (17.4 kg) for special version
Software included
  • API
  • Communication Test